1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to the fabrication of metal gate electrodes used in semiconductor devices.
2. Description of the Related Art
As the size and scaling of semiconductor device technology is reduced, aspects of device design and fabrication that previously gave rise to only second-order effects in long-channel devices can no longer be ignored. For example, the reduced scaling of channel length and gate oxide thickness in a conventional MOS transistor exacerbates problems of polysilicon gate depletion, high gate resistance, high gate tunneling leakage current and dopant (i.e., boron) penetration into the channel region of the device. As a result, CMOS technology is increasingly replacing silicon dioxide gate dielectrics and polysilicon gate conductors with high dielectric constant (high-k) dielectrics in combination with metal gate electrodes formed from a gate stack of polysilicon and one or more metal layers. With such technologies, the metal gate layers not only obviate gate-depletion and boron-penetration effects, but also provide a significantly lower sheet resistance.
While high-k dielectrics in conjunction with metal gate electrodes advantageously exhibit improved transistor performance, the use of new metal layer technologies can create new technical challenges. For example, to optimize drain current and device performance and reduce the voltage threshold Vts, the desired effective work function for NMOS and PMOS gate electrodes must be near the conduction (valence) band edge of silicon, meaning that the metals used in NMOS transistors should have effective work functions near 4.1 eV and metals used in PMOS transistors should have effective work functions near 5.2 eV. Since it is difficult to find a material that can have its work function adjusted once it is deposited, conventional approaches for obtaining differentiated work functions have involved forming separate gate electrode layers, such as by removing a deposited first metal gate layer from the gate insulator to deposit a second metal gate layer having a different work function. Such processes can damage the gate insulator layer, leading to high leakage or reliability problems for the finally formed device. Other approaches for modulating the work function for NMOS and PMOS gate electrodes toward the silicon conduction band edge have deposited capping layers of La2O3 (nFET) and Al2O3 (pFET) on the high-k gate dielectric (e.g., HfO2), and then applying a high temperature process step to shift the threshold voltage to incorporate the La and Al into the high-k gate dielectric in the NMOS and PMOS areas, respectively. With CMOS fabrication flows, each oxide capping layer is patterned with resist and then removed with a wet etch that is selective to the high-k gate dielectric, but this integration scheme creates a number of processing problems, including resist undercut, resist lifting, resist removal without damaging the gate dielectric, and resist rework that shifts the voltage threshold.
Another method of incorporating the La and Al into the gate dielectric is to first deposit a thin capping layer of Al2O3 and a metal gate on top of a high-k gate dielectric, pattern the metal gate and then remove the metal and Al2O3 layers from the NMOS regions, and then deposit a thin NMOS capping layer of La2O3 and an NMOS metal gate layer. The order of this integration can be reversed such that the La2O3 and NMOS metals are deposited first. This scheme results in two gate stacks of unbalanced height which can be a major challenge for the subsequent gate etch process where, for example, the NMOS gate stack includes an La2O3/NMOS Metal layer stack, and the PMOS gate stack includes an Al2O3/PMOS Metal/La2O3/NMOS Metal layer stack.
Accordingly, a need exists for an improved metal gate electrode and manufacture method for incorporated very thin high-k gate dielectric materials in NMOS and PMOS devices having the work functions that are set near the silicon band edges for low voltage thresholds and improved device performance to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.